iMACAW @ DAC 2022

An In-Memory Architectures and Computing Applications Workshop

Sunday, July 10th, 2022 @ the Moscone Convention Center in San Francisco, CA, USA

The iMACAW aims at providing a forum to discuss In-Memory-Computing as an alternative architecture and its applications. We take a cross-technology approach covering works that use SRAM, DRAM, FLASH, RRAM, PCM, MRAM, and FeFET as their memory technology. The workshop features ten renowned speakers from academia and industry, plus a limited selection of best submissions.

Program

The proposed format for the workshop is a full-day workshop featuring:

High-Profile Speakers

Ten renowned scientists from academia and industry present their latest work

Panel Discussions

Two panel discussions on the latest challenges and the future of in-memory computing

Poster Sessions

A limited selection of submissions will present their recent work with attendees

Time Title Speaker
8:00-9:40 Session 1
8:00-8:10 Opening Remarks Organizers: A. Bosio, D. Fan, N. Taherinejad
8:10-8:40 In-Memory Computing Based Machine Learning Accelerators: Opportunities and Challenges Kaushik Roy, Purdue University
8:40-9:10 Challenges and trends of SRAM based Computing in Memory Marvin Chang, TSMC
9:10-9:40 Scalable design considerations for RRAM-based in-memory computing systems Wei Lu, University of Michigan
9:40-10:00 Coffee Break Poster Session
10:00-11:45 Session 2 and Panel Discussion
10:00-10:30 Resistive memory technology: from device technology to applications in computing Daniele Ielmini, Politecnico Milano
10:30-11:00 Computational Random Access Memory: Recent Progress of Technologies and Applications Jian-Ping Wang, University of Minnesota
11:00-11:45 Panel Discussion Morning Speakers
11:50-13:00 Lunch Break Poster Session
13:00-14:30 Session 3
13:00-13:30 In-memory computing for a more efficient and general AI Abu Sebastian, IBM
13:30-14:00 Processing in Memory on DRAM offers tremendous opportunities for enhancing efficient data bandwidth and subsequent energy savings Gilles Hamou, UPMEM
14:00-14:30 The Mythic M1076 Analog Matrix Processor for Edge AI Real-Time Video Analytics Dave Fick, Mythic
14:30-15:00 Coffee Break Poster Session
15:00-17:00 Session 4 and Panel Discussion
15:00-15:30 Ferroelectric-enabled energy-efficient non-volatile edge computing Ian O'Connor, École Central de Lyon
15:30-16:00 A Survey of MRAM-Centric Computing: From Near Memory to In Memory Weisheng Zhao, Beihang University
16:00-16:45 Panel Discussion Afternoon Speakers
16:45-16:55 Closing Remarks Organizers: A. Bosio, D. Fan, N. Taherinejad

Confirmed Speakers

The following presenters have already agreed to present their latest research at iMACAW.

Kaushik Roy

Kaushik Roy

Purdue University

In-Memory Computing Based Machine Learning Accelerators: Opportunities and Challenges

Abstract Traditional computing systems based on the von Neumann architecture are fundamentally bottlenecked by data transfers between processors and memory. The emergence of dataintensive workloads, such as machine learning (ML), creates an urgent need to address this bottleneck by designing computing platforms that utilize the principle of co-located memory and processing units. We present a comprehensive overview of the emerging paradigm of computing using NVM and CMOS based crossbars for accelerating ML workloads. We describe the design principles of crossbars, including the devices and associated circuits that constitute them. We discuss intrinsic approximations arising from the device and circuit characteristics and study their functional impact on the MVM operation. Next, we present an overview of spatial architectures that exploit the high storage density of NVM crossbars. Furthermore, we elaborate on software frameworks that effectively capture device–circuit–architecture characteristics to evaluate the performance of large-scale deep neural networks (DNNs) using resistive crossbar-based hardware. Finally, we discuss open challenges and future research directions that need to be explored in order to realize the vision of resistive crossbars as the building blocks of future computing platforms.
Wei Lu

Wei Lu

University of Michigan

Scalable design considerations for RRAM-based in-memory computing systems

Abstract We will discuss recent progress in RRAM-based in-memory computing (IMC) modules, and approaches to build scalable systems that allow mapping of practical neural network models on a common fabric. Effects of device and circuit non-idealities on model performance will be discussed, along with potential solutions through architecture-aware training to minimize accuracy drop due to these non-ideal factors. Architecture-aware compression techniques that allow larger models to be mapped on the IMC system with a fixed on-chip memory capacity will be presented. Algorithm-architecture co-design that utilizes binarized networks to minimize device variation effects will also be discussed.
Daniele Ielmini

Daniele Ielmini

Politecnico Milano

Resistive memory technology: from device technology to applications in computing

Abstract Resistive-switching random-access memory (RRAM) is today emerged as one of the most mature and versatile device concepts for storage, memory and in-memory computing (IMC). Despite the relatively simple structure, RRAM materials can be engineered and optimized toward the desired behavior and performance. The underlying physical mechanisms for switching have been explored and clarified. Thanks to the relatively mature understanding of materials and mechanism, the industry has demonstrated high-density embedded RRAM, thus supporting the exploration of circuit-level applications in computing. This has resulted in a fast progress in the development of novel IMC paradigms. This talk will provide an overview about the status and challenges of RRAM for memory and computing. After reviewing the device concept and switching mechanism, the technological status will be summarized with reference to the most recent large-scale demonstrations of stand-alone and embedded memories. Then, the applications in computing will be reviewed, by covering four major trends, namely neuromorphic engineering, deep-learning accelerators, hardware security and general-purpose linear algebra. The main challenges for RRAM-based IMC will be finally discussed in terms of computing scaling, accuracy and energy efficiency.
Jian-Ping Wang

Jian-Ping Wang

University of Minnesota

Computational Random Access Memory: Recent Progress of Technologies and Applications

Abstract One key proposal for computation in memory is to directly use the memory cells to carry out the computation, e.g. compute at the data just mimicking the way our brain operation. We name this computing architecture as computational random access memory (CRAM), one of the most promising digital based in-memory computing (IMC) schemes. Spintronic devices, especially spin-orbit torque (SOT) devices, stand strongly for many IMC including CRAM architecture because of their superior endurance performance and potential energy efficiency. In this talk, we will briefly review the recent progress of spintronic technologies. Then we will report several recently reported applications of CRAM. First, we present a promising alternative to overcome scalability limitations, based on a network of in-memory SNN accelerators, which can reduce the energy consumption by up to 150 when compared to a representative ASIC solution. Second, we propose a non-volatile processing-in-memory (PIM) architecture which is extremely energy efficient, supports minimal overhead checkpointing for intermittent computing, can operate in a wide range of temperatures, and has a natural resilience to radiation. Third, we present CAMeleon - a novel energy-efficient compute substrate which can seamlessly be reconfigured to perform CAM operations in addition to logic and memory functions. CAMeleon has a similar level of latency to conventional CAM designs based on SRAM and emerging memory technologies (such as STT-MTJ, ReRAM and PCM), however, performs CAM operations more energy-efficiently, consumes less area, and can support traditional logic and memory functions beyond CAM operations on demand thanks to its reconfigurability. Forth, we report CRAM-Seq, an accelerator for RNA-Seq abundance quantification based on Computational RAM (CRAM) an in-memory processing substrate capable of high degree of parallel processing with very low energy consumption. Through hardware/software co-design, we demonstrate that CRAM-Seq outperforms a commonly used state-of-the-art software abundance quantification algorithm, Kallisto in terms of throughput and energy efficiency, while being highly scalable.
Weisheng Zhao

Weisheng Zhao

Beihang University

A Survey of MRAM-Centric Computing: From Near Memory to In Memory

Abstract Conventional von Neumann architecture suffers from bottlenecks in computing performance and power consumption due to frequent data exchange between memory and processing units. To overcome this issue, research on novel computing architectures including near-memory computing (NMC) and in-memory computing (IMC) has been accelerated based on emerging nonvolatile memory devices. Among various potential candidates, spintronic-based magnetic random-access memory (MRAM) has come into a research and development hotspot by virtue of its ultralow switching energy, nonvolatility, and superior endurance. This paper outlines the background, trends, and challenges involved in the development of MRAM-centric computing and highlights the recent prototypes and advances in applications based on MRAM-NMC and MRAM-IMC.
Abu Sebastian

Abu Sebastian

IBM, Zurich

In-memory computing for a more efficient and general AI

Abstract In this talk, I will give a status update on two overarching research goals we have been pursuing for several years. The first goal is to explore the limits of energy per operation when running AI algorithms such as deep learning (DL). In-memory computing (IMC) is a non-von Neumann compute paradigm that keeps alive the promise for 1fJ/Operation for DL. Attributes such as synaptic efficacy and plasticity can be implemented in place by exploiting the physical attributes of memory devices such as phase-change memory. I will provide an overview of the most advanced IMC cores based on phase-change memory integrated in 14nm CMOS technology node. The second goal is to develop algorithmic and architectural building blocks for a more efficient and general AI. I will present an overview of our recent contributions to computational approaches that transcend conventional DL such as neuro-vector symbolic architectures and more bio-realistic neural networks.
Marvin Chang

Marvin M. F. Chang

TSMC, Taiwan

Challenges and trends of SRAM based Computing in Memory

Abstract Compute-in-memory (CIM) is a promising candidate to breaking through the so-called memory wall bottleneck and improve the energy efficiency of AI edge devices. Among various memory devices, SRAM is a good candidate to enable CIM to use state-of-the art logic technologies and achieve high energy effiency with short latency. This talk outlines the challenges involved in the development of SRAM based CIM macros. This talk also reviews recent reported silicon-proven SRAM based CIM macros designed for multiplication-accumulation (MAC) operations used in deep learning based AI chips.
Ian O'Connor

Ian O'Connor

École Central de Lyon

Ferroelectric-enabled energy-efficient non-volatile edge computing

Abstract CMOS-compatible ferroelectric oxides are highly flexible and can be integrated both in the FEoL as FeFETs (Ferroelectric Field Effect Transistors) and in the BEoL as FeRAM (Ferroelectric Random Access Memories). Unlike existing memories, ferroelectric devices encode logic states in the remanent polarization of the ferroelectric oxide. They are currently emerging as a promising alternative to replace fast-access (less than µs) non-volatile memories, and demonstrate significantly better performance (high endurance, low write energy, etc.) with respect to existing solutions (Flash/MRAM/RRAM). The technology thus has immense potential to revolutionize machine learning at the edge in a wide variety of architectures for multiple AI applications. This talk will cover the principles, hardware demonstration and assessment of ferroelectric memory bitcells, non-volatile logic gates and reconfigurable circuits as well as a coefficient-programmable image filter, and will project the potential of such approaches to vector processing, machine learning and hardware security applications at the edge.
Dave Fick

David Fick

Mythic, Austin

The Mythic M1076 Analog Matrix Processor for Edge AI Real-Time Video Analytics

Abstract This presentation goes over the Mythic M1076 Analog Matrix Processor, a commercial analog compute engine (ACE) system for edge applications. The system has 79.69M 8-bit weights, a tiled architecture with 19,456 8-bit ADCs for parallel processing. This paper highlights some of the challenges and solutions to integrating analog compute into a complete system including power management, latency, dataflow, network mapping and compilation strategies. A pose estimator application is presented with batch 1 power and performance measurements.
Dave Fick is Mythic's CTO. He works with Mythic's technical leadership to spur innovation across a diverse technology stack, generating 16+ patents. He has a PhD in Computer Science & Eng from Michigan.
Gilles Hamou

Gilles Hamou

UPMEM, Grenoble

Processing in Memory on DRAM offers tremendous opportunities for enhancing efficient data bandwidth and subsequent energy savings

Abstract Designing into DRAM aims at leveraging massive data bandwidth in a massively distributed system. Solutions not only need to comply with DRAM architecture constraints but solutions also have to include a proper system orchestration. The benefits should come in terms of performance - speed and energy efficiency -, integrability, manufacturability and programmability. UPMEM exposes how we look at those challenges as its PIM-DRAM solution is effectively running various data intensive applications at scale. UPMEM also exposes the way forward to make intelligent memory a new standard for the processing industry.

Call for Submission

Submit an abstract to have a chance at presenting your work at iMACAW

Please submit an extended abstract up to 2 pages using the IEEE conference format to be considered for presenting your work as a poster and interact with workshop attendees during the poster sessions. DAC will not produce proceedings for workshops, however, the workshop organizers collect the camera-ready submissions and publish them on the workshop website.
Submission Link: https://easychair.org/my/conference?conf=imacaw22


Timeline:

Submission deadline (extended):15/March/2022 1/April/2022
Notification of acceptance: 15/April/2022
Final poster submission: 5/July/2022

* All deadlines are until the end of that day, anywhere on earth

Organizers

Feel free to contact us for any questions or concerns