4pm Central European time is (usually) 7am Pacific time and 11pm Beijing time
Given the recent comeback of processing in memory accelerators, it is important to notice all aspects of their development, in frequently overlooked aspects that have a major impact on the final performance. In this talk we discuss several of these details, like code offloading, compiler and operating system support, agressive data locality exploitation, high cost of host hardware modifications and plug and play alternatives, and finally partitioning and supporting multiple processes in a single memory device targeting multicore architectures. We also discuss some solutions and strategies that can lead to new research avenues.
Luigi Carro received the Electrical Engineering and the MSc degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the Reseach and Development group. In 1996 he received the Dr. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a full professor at the Applied Informatics Department at the Informatics Institute of UFRGS, in charge of Computer Architecture and Organization. He has advised more than 20 graduate students, and has published more than 150 technical papers on those topics. He has authored the book Digital systems Design and Prototyping (2001-in Portuguese) and is the co-author of Fault-Tolerance Techniques for SRAM-based FPGAs (2006-Springer), Dynamic Reconfigurable Architectures and Transparent optimization Techniques (2010-Springer) and Adaptive Systems (Springer 2012). In 2007 he received the prize FAPERGS - Researcher of the year in Computer Science. His most updated resume is located in http://lattes.cnpq.br/8544491643812450. For the latest news, please check www.inf.ufrgs.br/~carro
Petar Radojkovic received the MSc degree in computer science from the University of Belgrade, Belgrade, Serbia, and the MSc and PhD degree in computer architecture from the Universitat Politecnica de Catalunya, Barcelona, Spain. He is currently the Memory systems team leader at the Barcelona Supercomputing Center, and PI of BSC collaboration with Micron Technologies US and Huawei China. He was also leading a multi-project collaboration between the BSC and Samsung Electronics, Korea.
David has been a CNRS research scientist (equivalent to assistant professor) in the ADAC Group at LIRMM, France, since January 2017. Previously, he was a post-doctoral researcher at the EPFL School of Computer and Communication Sciences, Switzerland, where he joined the Processor Architecture Laboratory (LAP) in November 2010. Even longer ago, he conducted his doctoral research at IMEC, Belgium, receiving a Ph.D. in Engineering from the KU Leuven in 2010.
His research interests include hardware and software techniques for increasing computational efficiency in next-generation digital computers, with a particular focus on memory systems for multi-core architectures and programmable accelerators for machine learning applications.
For more information, please see https://www.lirmm.fr/david-novo/