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An introduction to MiM webinars host.

Dr. Nima TaheriNejad Nima's Picture

has PhD in Electrical and Computer Engineering from University of British Columbia (UBC), Vancouver, Canada. He is currently an assistant professor in TU Wien (formerly known also as Technical University of Vienna). Nima has published two books and more than 60 peer-reviewed articles, and has served as a reviewer and an editor of various journals and conferences. He has also been an organizer and a chair of various conferences and workshops. Nima has received several awards and scholarships from universities, conferences, and competitions he has attended. For more detailed information please visit his website.

Nima's interest in in-memory computing has peaked during last years. His work in this field is focused on design and implementation of memristive in-memory computing circuits and systems. Below you find a list of his and his team's publications related to in-memory computing.

Related publications since 2015

Used Tags: [J] Peer-reviewed Journal Papers, [C] Peer-reviewed Conference Papers, [B] Books, [P] Patents, [M] Other Publications.

  1. [C8] R. Rahimi Disfani, N. Taherinejad and M. Valinataj, “Operational Conditions Analysis for Memristive Stateful Logics - a Study on Imply and TMSL”, 20th IEEE International NEWCAS Conference, pp. 1-5, 2022.
  2. [J7] M. R. Alam, M. H. Najafi, N. Taherinejad, M. Imani, and R.Gottumukkala,, “Stochastic Computing in Beyond Von-Neumann Era: Processing Bit-Streams in Memristive Memory”, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), pp. 1-5, 2022.
  3. [J6] M. R. Alam, M. H. Najafi and N. Taherinejad, “Sorting in Memristive Memory”, ACM Journal on Emerging Technologies in Computing Systems, pp. 1-20, 2022.
  4. [C7] S. E. Fatemieh, M. R. Reshadinezhad and N. Taherinejad, “Approximate In-Memory Computing Using Memristive Imply Logic and its Application to Image Processing”, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2022.
  5. [M3] D. Radakovits and N. Taherinejad, “BEhavioral Leakage and IntEr-cycle Variability Emulator model for ReRAMs (BELIEVER)”, arXiv:2103.04179, pp. 1-13, 2021.
  6. [J5] N. Taherinejad, “SIXOR: Single-cycle In-memristor XOR”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 1-11, 2021. Paper & Simulation Files
  7. [M2] S. M. Laube and N. Taherinejad, “Device Variability Analysis for Memristive Material Implication”, arXiv:2101.07231, pp. 1-12, 2021.
  8. [J4] M. R. Alam, M. H. Najafi and N. Taherinejad, “Exact Stochastic Computing Multiplication in Memristive Memory”, IEEE Design and Test, pp. 1-8, 2021.
  9. [M1] M. R. Alam, M. H. Najafi and N. Taherinejad, “Sorting in Memristive Memory”, arXiv:2012.09918, pp. 1-10, 2020.
  10. [J3] D. Radakovits, N. Taherinejad, M. Cai, T. Delaroche, and S. Mirabbasi, “A Memristive Multiplier using Semi-Serial IMPLY-based Adder”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1495-1506, 2020.
  11. [C6] M. R. Alam, M. H. Najafi and N. Taherinejad, “Exact In-Memory Multiplication Based on Deterministic Stochastic Computing”, 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020.
  12. [J2] S. G. Rohani N. Taherinejad, D. Radakovits, “A Semi-Parallel Full-Adder in IMPLY Logic”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 28, no.1, pp. 297-301, 2020.
  13. [J1] N. Taherinejad and D. Radakovits, “From behavioral design of memristive circuits and systems to physical implementations”, IEEE Circuit and Systems (CAS) Magazine, vol. 19(4), pp. 6-18, 2019.
  14. [C5] N. Taherinejad, T. Delaroche, D. Radakovits, and S. Mirabbasi, “A semi-serial topology for compact and fast IMPLY-based memristive full adders”, IEEE New Circuits and Systems symposium (NewCAS), pp. 1-4, 2019.
  15. [C4] D. Radakovits and N. Taherinejad, “Implementation and characterization of a memristive memory system”, In 2019 IEEE 32nd Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1-5, May 2019.
  16. [C3] S. Rohani G., N. Taherinejad, “An Improved Algorithm for IMPLY Logic Based Memristive Full-Adder”, 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1-4, 2017.
  17. [C2] N. Taherinejad, S. Manoj P. D., M. Rathmair, A. Jantsch, “Fully digital write-in scheme for multi-bit memristive storage”, 13th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), Mexico City, Mexico, pp. 1-6, 2016.
  18. [C1] N. Taherinejad, S. Manoj P. D., A. Jantsch, “Memristors' Potential for Multi-Bit Storage and Pattern Learning”, IEEE Proceedings of the 9th European Modelling Symposium (EMS 2015), pp. 450-455, 2015.