Visitenkarte

Univ.Prof. Dipl.-Ing. Dr.techn. Axel Jantsch ,
Univ.Prof. Dipl.-Ing. Dr.techn. Axel Jantsch

Kontaktinformation

Telefon:
+43 1 58801 38415
E-Mail:
axel.jantsch@tuwien.ac.at
Raum:
CA0231
TISS:
TISS

Weitere Informationen:

A full list of publications is on my home page, where you also find a list of recent presentations.

Aufklappen um alle Publikationen (TU Wien) zu sehen

Alle Publikationen

  • A. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, H. Tenhunen (Hrsg.), The Dark Side of Silicon, Springer, 2016, S. 250.
  • S. Liu, A. Jantsch, Z. Lu, A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Bd. 22, Nr. 10, 2014, S. 2229 - 2233.
  • X. Chen, Z. Lu, A. Jantsch, S. Chen, Y. Guo, H. Chen, Performance Analysis of Homogeneous On-chip Large-scale Parallel Computing Architectures for Data-parallel Applications. Journal of Electrical and Computer Engineering, Bd. 2015, 2015, S. 1 - 20.
  • N. Dutt, A. Jantsch, S. Sarma, Towards Smart Embedded Systems: A Self-Aware System-on-Chip Perspective. ACM Transactions on Embedded Computing Systems, Bd. 14, 2015, S. 1 - 27.
  • F. Jafari, Z. Lu, A. Jantsch, Least Upper Delay Bound for {VBR} Flows in Networks-on-Chip with Virtual Channels. Design Automation for Embedded Systems, Bd. 20, Nr. 3, 2015, S. 1 - 33.
  • S. Liu, Z. Lu, A. Jantsch, MultiCS: Circuit switched NoC with multiple sub-networks and 4 sub-channels. Journal of Systems Architecture, Bd. 61, Nr. 9, 2015, S. 423 - 434.
  • J. Preden, K. Tammemäe, A. Jantsch, M. Leier, A. Riid, E. Callis, The benefits of awareness and attention in fog and mist computing. IEEE Computer, Bd. 48, Nr. 7, 2015, S. 37 - 45.
  • A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, V. S. Veeravalli, Building reliable systems-on-chip in nanoscale technologies. E&I Elektrotechnik und Informationstechnik, Bd. 132, Nr. 6, 2015, S. 301 - 306.
  • A. Weldezion, M. Grange, A. Jantsch, H. Tenhunen, D. Pamunuwa, Zero-Load Predictive Model for Performance Analysis in Deflection Routing {NoCs}. Microprocessors and Microsystems, Bd. 39, Nr. 8, 2015, S. 634 - 647.
  • L. Huang, J. Wang, M. Ebrahimi, M. Daneshtalab, X. Zhang, G. Li, A. Jantsch, Non-blocking Testing for Network-on-Chip. IEEE Transactions on Computers, Bd. 65, Nr. 3, 2016, S. 679 - 692.
  • F. Jafari, A. Jantsch, Z. Lu, Weighted Round Robin Configuration for Worst-Case Delay Optimization in {N}etwork-on-{C}hip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Bd. 24, Nr. 12, 2016, S. 3387 - 3400.
  • J. Wang, L. Huang, G. Li, A. Jantsch, Calculation of delivery rate in fault-tolerant network-on-chips. Electronics Letters, Bd. 52, Nr. 7, 2016, S. 546 - 548.
  • M. Haghbayan, A. Miele, A. Rahmani, P. Liljeberg, A. Jantsch, C. Bolchini, H. Tenhunen, Can Dark Silicon Be Exploited to Prolong System Lifetime?. Ieee Design & Test, Bd. 34, Nr. 2, 2017, S. 51 - 59.
  • A. Jantsch, N. Dutt, A. Rahmani, Self-awareness in systems on chip. Ieee Design & Test, Bd. 34, Nr. 6, 2017, S. 1 - 19.
  • A. Kanduri, M. Haghbayan, A. Rahmani, P. Liljeberg, A. Jantsch, H. Tenhunen, N. Dutt, Accuracy aware power management for many-core systems running error resilient applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Bd. 25, Nr. 10, 2017, S. 2749 - 2762.
  • A. Rahmani, M. Haghbayan, P. Liljeberg, A. Jantsch, H. Tenhunen, Reliability-aware runtime power management for many-core systems in the dark silicon era.. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Bd. 25, Nr. 2, 2017, S. 427 - 440.
  • A. Rahmani, A. Jantsch, N. Dutt, HDGM: Hierarchical dynamic goal management for many-core resource allocation. Embedded Systems, Bd. PP, Nr. 99, 2017, S. 1 - 4.
  • J. Wang, M. Ebrahimi, L. Huang, Q. Li, G. Li, A. Jantsch, Minimizing the system impact of router faults by means of reconfiguration and adaptive routing. Microprocessors and Microsystems, Bd. 51, 2017, S. 252 - 263.
  • A. Kanduri, M.-H. Haghbayan, A. Rahmani, M. Shafique, A. Jantsch, P. Liljeberg, adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning. IEEE Transactions on Computers, Bd. 67, Nr. 8, 2018, S. 1062 - 1077.
  • T. Mueck, B. Donyanavard, K. Moazzemi, A. Rahmani, A. Jantsch, N. Dutt, Design Methodology for Responsive and Robust MIMO Control of Heterogeneous Multicores. IEEE Transactions on Multi-Scale Computing Systems, Bd. 1, Nr. 1, 2018, S. 1 - 9.
  • S. Pagani, S. Pudukotai Dinakarrao, A. Jantsch, J. Henkel, Machine learning for power, energy, and thermal management on multi-core processors: A survey.. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Bd. 1, Nr. 1, 2018, S. 1 - 18.
  • S. Pudukotai Dinakarrao, A. Jantsch, M. Shafique, SmartDPM: Machine Learning-based Dynamic Power Management for Multi-Core Microprocessors. ASP Journal of Low Power Electronics (JOLPE), Bd. 14, Nr. 4, 2018, S. 460 - 474.
  • L. Siafara, H. Kholerdi, A. Bratukhin, N. TaheriNejad, A. Jantsch, SAMBA - An architecture for adaptive cognitive control of distributed Cyber-Physical Production Systems based on its self-awareness.. E&I Elektrotechnik und Informationstechnik, Bd. 135, Nr. 3, 2018, S. 270 - 277.
  • J. Wang, M. Ebrahimi, L. Huang, X. Xie, Q. Li, G. Li, A. Jantsch, Efficient Design-for-Test Approach for Networks-on-Chip. IEEE Transactions on Computers, Bd. 1, Nr. 1, 2018, S. 1 - 16.
  • M. Wess, S. Pudukotai Dinakarrao, A. Jantsch, Weighted Quantization-Regularization in DNNs for Weight Memory Minimization towards HW Implementation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Bd. 37, Nr. 11, 2018, S. 2929 - 2939.
  • M. Götzinger, N. TaheriNejad, H. Kholerdi, A. Jantsch, E. Willegger, T. Glatzl, A. M. Rahmani, T. Sauter, P. Liljeberg, Model-free condition monitoring with confidence. International Journal of Computer Integrated Manufacturing, Bd. 32, Nr. 4-5, 2019, S. 466 - 481.
  • S. Pudukotai Dinakarrao, A. Jantsch, M. Shafique, Computer-aided arrhythmia diagnosis with bio-signal processing: A survey of trends and techniques. Acm Computing Surveys, Bd. 52, Nr. 2, 2019, S. 1 - 37.
  • M. Ruaro, A. Jantsch, F. Moraes, Self-adaptive QoS management of computation and communication resources in many-core SoCs. ACM Transactions on Embedded Computing Systems, Bd. 18, Nr. 4, 2019, S. 1 - 21.
  • K. Bellmann, L. Christopher, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, N. TaheriNejad, P. Lewis, M. Platzner, K. Tammemäe, Self-aware Cyber-Physical Systems. ACM Transactions on Cyber-Physical Systems, Bd. 4, Nr. 38, 2020, S. 1 - 26.
  • M. Götzinger, D. Juhasz, N. TaheriNejad, E. Willegger, B. Tutzer, P. Liljeberg, A. Jantsch, A. M. Rahmani, RoSA: A Framework for Modeling Self-Awareness in Cyber-Physical Systems. IEEE Access, Bd. 8, 2020, S. 141373 - 141394.
  • H. Hoffmann, A. Jantsch, N. Dutt, Embodied Self-Aware Computing Systems. Proceedings of the IEEE, Bd. 108, Nr. 7, 2020, S. 1027 - 1046.
  • M. Wess, M. Ivanov, C. Unger, A. Nookala, A. Wendt, A. Jantsch, ANNETTE: Accurate Neural Network Execution Time Estimation With Stacked Models. IEEE Access, Bd. 9, 2021, S. 3545 - 3556.
  • A. Kanduri, M. Haghbayan, A. Rahmani, P. Liljeberg, A. Jantsch, H. Tenhunen, Dark Silicon Patterning: Efficient Power Utilization through Run-time Mapping, in The Dark Side of Silicon, Springer, 2016, S. .
  • A. Kanduri, A. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, H. Tenhunen, Dark Silicon - Challenges and Opportunities, in The Dark Side of Silicon, Springer, 2016, S. .
  • A. Rahmani, M. Haghbayan, P. Liljeberg, A. Jantsch, H. Tenhunen, Multi-Objective Power Management for {CMPs} in the Dark Silicon Age, in The Dark Side of Silicon, Springer, 2016, S. .
  • I. Sander, A. Jantsch, S. Attarzadeh-Niaki, Forsyde: System design using a functional language and models of computation, in Handbook of Hardware/Software Codesign, Springer, 2017, S. 99 - 140.
  • H. Kholerdi, N. TaheriNejad, A. Jantsch, Enhancement of Classification of Small Data Sets Using Self-Awareness - an Iris Flower Case-Study, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE International Symposium on Circuits and Systems (ISCAS), 2018, S. 1 - 5.
  • M. Mosbeck, D. Hauer, A. Jantsch, VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments, 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), IEEE, 2018, S. .
  • S. Pudukotai Dinakarrao, A. Jantsch, Arrhythmia Detection with Digital Hardware by Learning {ECG} Signal, ACM Great Lakes Symposium on VLSI 2018, ACM Digital Library, 2018, S. 495 - 498.
  • A. Anzanpour, H. Rashid, A. Rahmani, A. Jantsch, N. Dutt, P. Liljeberg, Energy-efficient and reliable wearable internet-of-things through fog-assisted dynamic goal management, The 10th International Conference on Ambient Systems, Networks and Technologies (ANT), Academic Press / Elsevier, 2019, S. 493 - 500.
  • A. Jantsch, Towards a Formal Model of Recursive Self-Reflection, Workshop on Autonomous Systems Design (ASD 2019)}, Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2019, S. 1 - 15.
  • E. Shamsa, A. Kanduri, A. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt, Goal-driven autonomy for efficient on-chip resource management: Transforming objectives to goals., 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, S. 1 - 6.
  • N. TaheriNejad, P. Lewis, A. Jantsch, A. Rahmani, L. Esterle, Resource Constrained Self-Aware Cyber-Physical Systems (Tutorial), 2019 IEEE 4th International Workshops on Foundations and Applications of Self* Systems (FAS*W), IEEE, 2019, S. 259 - 260.
  • D. Bechtold, A. Wendt, A. Jantsch, Evaluation of Reinforcement Learning Methods for a Self-learning System, Proceedings of the 12th International Conference on Agents and Artificial Intelligence (ICAART 2020), SCITEPRESS - Science and Technology Publications, Lda., 2020, S. 36 - 47.
  • A. Wendt, S. Kollmann, A. Bratukhin, A. Estaji, T. Sauter, A. Jantsch, Cognitive Architectures for Process Monitoring - an Analysis, 2020 IEEE 18th International Conference on Industrial Informatics (INDIN), IEEE Industrial Electronics Society, 2020, S. 167 - 173.
  • B. Haas, A. Wendt, A. Jantsch, M. Wess, Neural Network Compression Through Shunt Connections and Knowledge Distillation for Semantic Segmentation Problems, Artificial Intelligence Applications and Innovations, 17th IFIP WG 12.5 International Conference, Springer Nature Switzerland AG, 2021, S. 349 - 361.
  • M. Ebrahimi, J. Wang, L. Huang, M. Daneshtalab, A. Jantsch, Rescuing Healthy Cores Against Disabled Routers, in Proceedings of 2014 IEEE the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, S. 1 - 8.
  • A. Jantsch, K. Tammemäae, A Framework of Awareness for Artificial Subjects, in Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, ISSS+CODES, 2014, S. 20:1 - 20:3.
  • M. Haghbayan, A. Rahmani, A. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, H. Tenhunen, Silicon Aware Power Management for Manycore Systems under Dynamic Workloads, in Proceedings of the International Conference on Computer Design, 2014, S. 509 - 512.
  • X. Zhang, M. Ebrahimi, L. Huang, G. Li, A. Jantsch, A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs, in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), S. 5, Turku, 2015.
  • R. Ma, Z. Hui, A. Jantsch, A Packet-switched Interconnect for Many-core Systems with {BE} and {RT} Service, in Proceedings of the Design Automation and Test Europe Conference (DATE), S. 4, Grenoble, France, 2015.
  • A. Rahmani, H. Tenhunen, P. Liljeberg, A. Weldezion, S. Kanduru, J. Plosila, M. Haghbayan, A. Jantsch, Dynamic Power Management for Many-Core Platforms in the Dark Silicon Era: A Multi-Objective Control Approach, in Proceedings of the International Symposium on Low Power Electronics and Design, S. 6, Rom, Italy, 2015.
  • X. Chen, Z. Lu, A. Jantsch et al., Achieving Memory Access Equalization via Round-trip Routing Latency Prediction in 3D Many-core NoCs, in Proceedings of IEEE Annual Symposium on VLSI (ISVLSI), S. 6, Montpellier, 2015.
  • J. Wang, M. Ebrahimi, L. Huang, A. Jantsch, G. Li, Design of Fault-Tolerant and Reliable Networks-on-Chip, in Proceedings of IEEE Annual Symposium on VLSI (ISVLSI), S. 6, Montpellier, 2015.
  • M. Haghbayan, A. Kanduri, A. Rahmani, P. Liljeberg, A. Jantsch, H. Tenhunen, MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip, in Proceedings of the International Symposium on Networks on Chip, S. 8, Vancouver, Canada, 2015.
  • S. Liu, Z. Lu, A. Jantsch, Highway in TDM NoCs, in NoCS, S. 8, Vancouver, Canada, 2015.
  • A. Kanduri, M. Haghbayan, A. Rahmani, P. Liljeberg, A. Jantsch, H. Tenhunen, Dark Silicon Aware Runtime Mapping for Many-core Systems: A Patterning Approach, in roceedings of the International Conference on Computer Design (ICCD), S. 8, New York, USA, 2015.
  • N. TaheriNejad, S. Pudukotai Dinakarrao, A. Jantsch, Memristors' Potential for Multi-Bit Storage and Pattern Learning, in IEEE Proceedings of the 9th European Modelling Symposium (EMS 2015), S. 6, Madrid, Spain, 2015.
  • N. Dutt, A. Jantsch, S. Sarma, Self-aware cyber-physical systems-on-chip, in Proceedings of the International Conference for Computer Aided Design (invited), S. 5, Austin, Texas, 2015.
  • Y. Zhang, L. Li, A. Jantsch, Z. Lu, M. Gao, Y. Fu, H. Pan, Exploring Stacked Main Memory Architecture for 3D GPGPUs, in IEEE International Conference on ASIC (ASICON), S. 4, Chengdu, 2015.
  • J. Wang, L. Huang, M. Ebrahimi, Q. Li, A. Jantsch, G. Li, VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping, in Proceedings of the Third ACM International Workshop on Many-core Embedded Systems, S. 8, Seoul, Sout Korea, 2016.
  • N. TaheriNejad, A. Jantsch, D. Pollreisz, Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example, in Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016, S. 117 - 124.
  • M. Götzinger, A. Rahmani, M. Pongratz, P. Liljeberg, A. Jantsch, H. Tenhunen, The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems, in Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (IEEE MCSoC 2016), S. 8, Lyon, 2016.
  • N. TaheriNejad, S. Pudukotai Dinakarrao, M. Rathmair, A. Jantsch, Fully digital write-in scheme for multi-bit memristive storage, in 13th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2016, S. 1 - 6.
  • J. Wang, L. Huang, Q. Li, G. Li, A. Jantsch, Optimizing the Location of {ECC} Protection in Network-on-Chip, in Proceeding of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), S. 8, USA, 2016.
  • C. Krieg, C. Wolf, A. Jantsch, Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow, in Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016, S. 43:1 - 43:8.
  • M. Götzinger, N. TaheriNejad, A. Rahmani, P. Liljeberg, A. Jantsch, H. Tenhunen, Enhancing the Early Warning Score System Using Data Confidence, in 6th EAI International Conference on Wireless Mobile Communication and Healthcare, S. 8, Milan, 2016.
  • M. Götzinger, M. Pongratz, A. Rahmani, A. Jantsch: Parallelized Flight Path Prediction Using a Graphics Processing Unit. in Proceedings of the 12th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications. (VISAPP17), S. 8, Porto, Portugal, 2017.
  • A. Anzanpour, I. Azimi, M. Götzinger, A. Rahmani, N. TaheriNejad, P. Liljeberg, A. Jantsch, N. Dutt, Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics, in Proceedings of the Internation Conference of Design, Automation and Test in Europe. (DATE17), S. 6, Lausanne, Switzerland, 2017.
  • C. Radojicic, C. Grimm, A. Jantsch, M. Rathmair, Towards verification of uncertain cyber-physical systems, in Proceedings 3rd International Workshop on Symbolic and Numerical Methods for Reachability Analysis, S. 17, Uppsala, 2017.
  • M. Götzinger, N. TaheriNejad, H. Kholerdi, A. Jantsch, On the Design of Context-Aware Health Monitoring without a Priori Knowledge; an AC-Motor Case-Study, in The 30th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), S. 5, Windsor, 2017.
  • M. Wess, S. Pudukotai Dinakarrao, A. Jantsch, Neural network based ECG anomaly detection on FPGA and trade-off analysis, in IEEE International Symposium on Circuits and Systems (ISCAS), 2017, S. 1 - 4.
  • C. Krieg, C. Wolf, A. Jantsch, T. Zseby, Toggle MUX: How X-optimism can lead to malicious hardware, in Proceedins of the Design Automation Conference (DAC), S. 6, Austin, 2017.
  • N. Dutt, A. Rahmani, A. Jantsch, Empowering autonomy through self-awareness in MPSoCs, in Proceedings of the IEEE NEWCAS Conference, 2017, S. 73 - 76.
  • L. Siafara, H. Kholerdi, A. Bratukhin, N. TaheriNejad, A. Wendt, A. Jantsch, A. Treytl, T. Sauter: SAMBA: A Self-Aware Health Monitoring Architecture for Distributed Industrial Systems. in IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, S. 6, Beijing, China, 2017.
  • A. Jantsch, A. Anzanpour, H. Kholerdi, I. Azimi, L. Siafara, A. Rahmani, N. TaheriNejad, P. Liljeberg, N. Dutt, Hierarchical Dynamic Goal Management for IoT Systems, in Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), 2018, S. 370 - 375.
  • M. Mosbeck, M. Meisel, M. Rathmair, A. Jantsch, VELS- VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Customized Tasks for Hardware Modeling Courses, in MESS18 Microelectronic Systems Symposium, 2018, S. 34.
  • R. Arbaud, D. Juhasz, A. Jantsch, Resource Management for Mixed-Criticality Systems on Multi-Core Platforms with Focus on Communication, in Proceedings of the 2018 21st Euromicro Conference on Digital System Design, 2018, S. 627 - 641.
  • K. Moazzemi, A. Kanduri, D. Juhasz, A. Miele, A. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt, Trends in On-Chip Dynamic Resource Management, in Proceedings of the 2018 21st Euromicro Conference on Digital System Design, 2018, S. 62 - 69.
  • M. Götzinger, E. Willegger, N. TaheriNejad, A. Jantsch, T. Sauter, T. Glatzl, P. Liljeberg, Applicability of Context-Aware Health Monitoring to Hydraulic Circuits, in Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society The IECON 2018 (invited), 2018, S. .
  • I. H. Abbassi, F. Khalid, S. Rehman, A. M. Kamboh, A. Jantsch, S. Garg, M. Shafique, TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint, in Proceedings of 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE), 2019, S. 914 - 919.
  • B. Tutzer, C. Krieg, C. Wolf, A. Jantsch, Python Wraps Yosys for Rapid Open-Source EDA Application Development, in Proceedings of the First Workshop on Open-Source Design Automation (OSDA) 2019, S. 4, Florenz, 2019.
  • D. Juhasz, A. Jantsch, Dynamic Constraints for Mixed-Criticality Systems, in Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019, S. 25 - 30.
  • M. Hanif, M. Akbar, R. Ahmed, S. Rehman, A. Jantsch, M. Shafique, MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks, in Proceeding of 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'19), 2019, S. 1 - 6.
  • D. Hauer, D. Ratasich, L. Krammer, A. Jantsch, A Methodology for Resilient Control and Monitoring in Smart Grids, in 2020 IEEE International Conference on Industrial Technology (ICIT), 2020, S. 589 - 594.
  • A. Jantsch, Critical research areas driven by industry transformations, in Presentation: Design Automation and Test Europe (DATE) (invited), Grenoble, France.
  • A. Jantsch, N. Dutt, Self-awareness in cyber-physical systems, in Presentation: HiPEAC Computing Week (invited), Oslo.
  • A. Jantsch, The it and the self - challenges and opportunities in cyber-physical systems, in Presentation: EIT Summer School on Cyber Physical Systems (invited), Stockholm.
  • M. Mosbeck, D. Hauer, A. Jantsch, VELS: VHDL E-Learning System, in Presentation: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estland.
  • J. Glaser, Design Methodology for Custom Reconfigurable Logic Architectures, Supervisor: C. Grimm, A. Jantsch, E384, 2015.
  • M. Perner, Fault-Tolerant Clock Distribution in Grid-Like Networks, Supervisor: U. Schmid, A. Jantsch, M. Krstic, Institut für Computer Engineering (E191-02), 2019.
  • J.G.O. Wenninger, A. Jantsch, M. Rathmair, C. Halmdienst, G. Zucker, M. Blöchle, Endbericht extrACT -- Automatische Funktions- und Ertragskontrolle für thermische Gebäudesysteme - Effizienzsteigerung Datenextraktion, tech. report, Institute of Computer Technology, Vienna University of Technology, for: FFG, 2015.
  • M. Ivanov, M. Wess, A. Jantsch, Embedded Machine Learning Demonstrator, tech. report, Institute of Computer Technology, Vienna University of Technology, 2021.